Field
Embodiments described herein generally relate to methods for forming a semiconductor device having an air gap. More specifically, embodiments described herein relate to an integrated metal spacer and air gap interconnect.
Description of the Related Art
For advanced node technologies, interconnect RC delay (switching performance) and power dampening due to capacitance are critical thresholds of device performance. Given the scaling performance limitations of conventional low-k materials in lowering the dielectric constant (k value) as a result of compromising mechanical strength and current leakage performance, one promising candidate for capacitance scaling includes the adoption of air gaps between metal wiring. Air gaps, which have a k value near 1.0, help reduce the overall effective k value to acceptable levels within the device. However, air gap integration requires additional processing steps, including exclusion mask lithography, dielectric recess, liner deposition, dielectric deposition, dielectric chemical mechanical polishing (CMP), etc. These additional steps increase the cost of integrating air gaps and reduce the benefits and acceptance of air gap technologies.
In addition, double patterning is generally utilized instead of single print patterning to form air gaps. Some examples of double patterning include litho-etch-litho-etch (LELE) and spacer aligned double patterning (SADP). These double patterning techniques not only require additional exposure and etch processes, but also require masks to define connectors and line ends. The double patterning processes transfer the desired design to the final product, but do so with increased cost and reduced efficiency.
Thus, what is needed are improved methods for forming air gap interconnect structures.